MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...

What's all the buzz on UVM? The quite successful 2011 Design and Verification Conference was held last week. The most prominent topic at the conference was the Universal Verification Methodology (UVM) ...

UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, ...

NAPA, CA--(Marketwired - Jun 24, 2014) - Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and ...

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...

The 90-minute tutorial focuses on the use of Easier UVM and SCE-MI to help teams get started with UVM and, importantly, to future-proof their UVM verification environments by making them ...