IEEE

Efficient Hardware Accelerator Design for AES Encryption Using High-Level Synthesis Techniques

Abstract: In this work, we present the design and implementation of a hardware accelerator for AES encryption and decryption using AMD Vitis HLS and Xilinx Vivado. The primary objective of this work ...
IEEE

Designing of AES-128 Encryption Algorithm Using System Verilog VLSI

Abstract: This paper details a comprehensive study on the implementation of the Advanced Encryption Standard (AES) using Very Large Scale Integration (VLSI) technology for the purpose of creating ...