Design-Reuse

Trace Based Approach for Unit Level Debug and Verification of C/C++ IP Models

Amongst various pre-silicon solutions, Software Simulation Platforms have always been the preferred environment due to early availability, ease of use, ease of access, lower cost as compared to FPGAs ...
EDN

I2C-Based Real Time Clock / Calendar – RTL Design and Verification

Designed the main architecture of ASIC IC PCF8583 by Philips Semiconductors. It involved writing time and calendar properties sent by I2C master onto an I2C based slave RAM.
Design-Reuse

A Platform Based SoC Design Environment

1 Dept. of Electronic and Computer Engineering, Korea Univ. 2 Korea semiconductor Intellectual Property Exchange Org. 3 Wireless SOC R&D Center, Mewtel Inc. We present a reusable integrated design ...
EDN

Tool aids RTL design quality, productivity

ActiveDesign with Behavioral Indexing provides behavior-based RTL analysis and verification for designers, improving design quality and designer productivity. Behavioral Indexing technology enables ...
Dhaka Tribune

CVES launches course on RTL design, verification and VLSI synthesis

The American International University-Bangladesh (AIUB) inaugurated a new professional industry-focused course titled “RTL Design, Verification, Synthesis and PnR for Digital VLSI Design” on October 5 ...