GitHub

FOUR_BIT_PARALLEL_ADDER

FOUR_BIT_PARALLEL_ADDER F1(a[0],b[0],cin,s[0],cout[0]); FOUR_BIT_PARALLEL_ADDER F2(a[1],b[1],cout[0],s[1],cout[1]); FOUR_BIT_PARALLEL_ADDER F3(a[2],b[2],cout[1],s[2 ...
Hackaday

2-bit Full Adder Using Just Thirty Six 555 Timers

This 2-bit adder was a lot of work to build. It uses a total of thirty-six 555 timers and it does have the option of adding or subtracting numbers. It’s a rather unorthodox use of the part, depending ...
IEEE

A 64 bit parallel CMOS adder for high performance processors

Abstract: A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 /spl mu/m 1-poly 5-metal CMOS technology. A new ...
Nature

Implementation of half adder and half subtractor with a simple and universal DNA-based platform

As a powerful material, DNA presents great advantages in the fabrication of molecular devices and higher-order logic circuits. Herein, by making use of the hybridization and displacement of DNA ...