GitHub

RISC-V-Tapeout-chip-program-week-1

Building upon the RISC-V learning journey, the focus of Week 1 . it was about the simulation and synthesis of both combinational and sequential circuit . This week was about the digital design ...
IEEE

Inverses of Linear Sequential Circuits

Abstract: Abstract—This paper states the necessary and sufficient conditions for the existence of a feedforward inverse for a feedforward linear sequential circuit and gives an implicit procedure for ...
IEEE

Efficient Designing Approach of Different Synchronous Cyclic Code Counters by Sequential Circuit Elements of a Novel Reversible Gate

Abstract: Reversible logic is widely being considered as the probable logic design style for implementation in modern nanotechnology, optical computing and quantum computing with least impact on ...
Design-Reuse

Designing low-power sequential circuits using clock gating

With shrinking technologies, rapid multiplication of clock frequencies, and increasing emphasis on power reduction, low-power design is taking on a vital role. Design teams can no longer afford to ...