EDN

PLL clock IC offers 10-ps rms jitter

The NB4N507A PLL clock IC generates a clock signal ranging from 50 to 200 MHz via an inexpensive reference crystal. The device offers an rms period jitter of less than 10 ps and an accuracy of 100 ppm ...
Design And Reuse

Creating a Frequency Plan for a System using a PLL

Perceptia Devices is an IP and design services provider, based in Sydney, Australia and Silicon Valley. It is focused on PLLs for RF systems and demanding clocking applications. Perceptia offers a ...
Design-Reuse

Auto Clock Generation in a SoC

This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting ...