Electronic Design

32-Bit Architecture Challenges 8-Bit Processors

Can developers utilize a 32-bit architecture with a clear upgrade path even when low power and compact size are high on the list of requirements? Arm Ltd. attempts to answer that question with its ...
Design-Reuse

Extending RISC-V ISA With a Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
Design-Reuse

Imperas delivers first RISC-V Simulator for new Vector and Bit Manipulation specifications to Lead Customers

Imperas leading simulation technology updated to include the latest ratified RISC-V specifications and new Vector and Bit Manipulation standard extensions. Used for RISC-V software development, ...
EDN

Building a 4-Bit Computer: Instruction Trade-offs

If you are limiting yourself to only 16 instructions, which ones should you chose, and how do you manage without the ones that fall by the wayside? In my previous column on our project to build a ...
Yahoo Finance

Andes Technology’s N25F RISC-V Processor Enables Superior Immersive Scenarios for ASPEED Technology’s Powerful Image Stitching SoC AST1230

Hsinchu, Taiwan, March 06, 2023 (GLOBE NEWSWIRE) -- Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor ...
EDN

Building a 4-Bit Computer: Assembly Language and Assembler (Part 1)

We’ve come to the point where we need to define an assembly language for our 4-Bit HRRG Computer, but first we need to consider certain concepts. These days, we are used to programming our computers ...
Hackaday

One Bit, One Instruction Discrete CPU

There is a certain benefit to being an early adopter. If you were around when Unix or MSDOS had a handful of commands, it wasn’t hard to learn. Then you learn new things as they come along. If you ...